To analyze failure caused in a semiconductor integrated circuit, the output of a signal based upon the input of the signal is monitored, and a position and a cause of the failure are estimated. An expected value of the output of the signal based upon the input of the signal can be calculated by a computer where functions of the integrated circuit are modeled and the same operation can be simulated. When the integrated circuit is normal, a value of an output signal from the integrated circuit coincides with the expected value calculated by the computer. Conversely, when the values do not coincide, it can be said that failure occurs. In the next step, it is estimated what sort of variation of the functional model formed by the computer (called a failure model) has the same output expected value as a signal output from the integrated circuit. When an output expected value of a certain failure model coincides with a value of an output signal from the integrated circuit, it can be said that the failure model is functionally equal to the failure of the integrated circuit. Hereby, the position and the cause of the failure can be analyzed.
To execute the above-mentioned analysis, a condition on which the operation of the integrated circuit is different from an expected value is required to be found. For example, it can be expected that as for failure (a short-circuit) that a value of a signal in a signal conductor is fixed to 0 or 1, the nonconformity of an output signal value and an expected value can be relatively easily found by increasing the variations of the combination with a value of an input signal to the integrated circuit. In the meantime, some failure is not revealed on conditions except a certain specific condition and an integrated circuit having the failure appears to function like a normal one. For example, failure caused because of power supply voltage, temperature, a frequency of a clock or power supply noise and others can be given. When such an integrated circuit is built in a product and is operated, a problem of the operation is observed. However, when the integrated circuit (the chip) is detached from the product for failure analysis and is operated in an LSI tester, an expected value of output coincides with all input signals and the integrated circuit is sometimes indistinguishable from normal LSI (nonreproduction of failure).
To reproduce failure, a condition of measurement is required to be made to approach an operating condition when the chip is built in the product. Therefore, the LSI tester is provided with a function for changing a condition such as power supply voltage, temperature and a frequency of a clock and efforts toward searching a condition on which the integrated circuit makes operation different from the expected value (reproducing failure) are made. However, in the current LSI tester, it is sometimes difficult to change a frequency of a clock, power supply noise and others out of causes that make failure revealed. For example, an LSI tester corresponding to a high-frequency clock is high-priced and in the current LSI tester, it is difficult to prepare an operating environment in which power supply noise when the integrated circuit is built in the product can be fully simulated.
Therefore, a trial for reproducing failure by making the integrated circuit operate in a state in which it is built in the product is proposed. A method of analyzing a position and a cause of failure with the integrated circuit built in the product is disclosed in Japanese Unexamined Patent Application Publication No. 2004-101203.